In semiconductor processing equipment RF bias is often applied to the pedestal. RF bias introduces an ion flux of a certain energy that impacts the surface of the wafer placed on the pedestal. Those energetic ions initiate ion-induced processes which are essential for semiconductor processing technology. For typical semiconductor processing chamber configuration RF bias induces a negative DC offset (DC self-bias) on a wafer.
Electrostatic chucks (“ESCs”) are commonly used for clamping the wafer on the pedestal. ESC provides a good and reliable thermal contact between the wafer and the pedestal and seals helium which is usually introduced to the backside of the wafer for better and more uniform heat transfer.
Generally, the electrostatic clamping force depends on the difference between the wafer potential and the potential of a DC electrode embedded in the ESC. The potential of the DC electrode is driven by an external power supply which is typically referenced to a ground potential, while wafer potential is defined by the DC self-bias induced by the RF power delivered to the plasma.
Direct in-situ measurement of wafer DC potential is often precluded by the ESC and pedestal design and process contamination requirements. Therefore it is usually measured indirectly using the data from the voltage-current (“V-I”) probe installed at the output of the RF match and a circuit model of the pedestal. In other words, wafer DC bias is typically calculated from the RF voltage, RF current and a phase shift between them at the match output using a circuit model which is specific to the chamber and pedestal design. Accuracy of wafer DC bias measurement is primarily defined by the adequacy of the circuit model. Accurate direct (ex-situ) measurements of the wafer DC self-bias need to be performed to calibrate and verify the circuit model.
An error in wafer DC self-bias measurement may result in a process shift, wafer loss (wafer sticking, high backside helium leak, etc.), or both. The incorrect measurement of wafer DC potential affects the reliability of chamber operation. The DC self-bias usually represents the mean energy of ions impinging the wafer surface. An error in wafer DC self-bias measurement may result in the incorrect determination of energy of ions impinging the wafer surface that may negatively impact process development.
A wafer DC potential may be directly measured using an external probe brought in a direct contact with the wafer surface. However, using the external probe may not be acceptable due to chamber contamination requirements. The external probe may also significantly perturb plasma. Furthermore, the external probe may create parasitic discharges in the feed through which may impact the measurement accuracy. Additionally, the external probe requires specialized test equipment and a chamber access port which may not be available.